Prof. Vassos Soteriou, an assistant professor in the Department of Electrical Engineering, Computer Engineering and Informatics at the Cyprus University of technology, received a High-Performance and Embedded Architectures and Compilers (HiPEAC) Paper Award from the HiPEAC Network of Excellence.
Prof. Soteriou, along with his post-doctoral fellow Dr. Arseniy Vitkovskiy and colleagues from the Texas A&M University Prof. Paul Gratz and his student Dr. Hyungjun Kim, received the award for their paper titled “Use it or Lose it: Wear-out and Lifetime in Future Chip Multiprocessors,” which appeared in the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2013.
The paper discusses how Moore’s Law scaling is continuing to yield even higher transistor density with each succeeding process generation, leading to today’s multi-core Chip Multi-Processors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep sub-micron CMOS process technology is marred by increasing susceptibility to wearout.
The Research Team argues that prolonged operational stress gives rise to accelerated wearout and failure, due to several physical failure mechanisms, including Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults.
While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic for the system, a single fault in the inter-processor Network-on-Chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In their paper, critical path models for HCI- and NBTI-induced wear due to the actual stresses caused by real workloads are developed and applied onto the interconnect microarchitecture. A key finding from this modeling is that wearout in the CMP on-chip interconnect is correlated with lack of load observed in the NoC routers, rather than high load. A novel wearout-decelerating scheme in which routers under low load have their wearout-sensitive components exercised, without significantly impacting cycle time, pipeline depth, area or power consumption of the overall router is developed, which shows that the proposed design yields a 13.8x-65x increase in CMP lifetime.
Soteriou and Vitkovskiy receive award from the HiPEAC Network of Excellence
Prof. Vassos Soteriou, an assistant professor in the Department of Electrical Engineering, Computer Engineering and Informatics at the Cyprus University of technology, received a High-Performance and Embedded Architectures and Compilers (HiPEAC) Paper Award from the HiPEAC Network of Excellence.
Prof. Soteriou, along with his post-doctoral fellow Dr. Arseniy Vitkovskiy and colleagues from the Texas A&M University Prof. Paul Gratz and his student Dr. Hyungjun Kim, received the award for their paper titled “Use it or Lose it: Wear-out and Lifetime in Future Chip Multiprocessors,” which appeared in the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2013.
The paper discusses how Moore’s Law scaling is continuing to yield even higher transistor density with each succeeding process generation, leading to today’s multi-core Chip Multi-Processors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep sub-micron CMOS process technology is marred by increasing susceptibility to wearout.
The Research Team argues that prolonged operational stress gives rise to accelerated wearout and failure, due to several physical failure mechanisms, including Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults.
While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic for the system, a single fault in the inter-processor Network-on-Chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In their paper, critical path models for HCI- and NBTI-induced wear due to the actual stresses caused by real workloads are developed and applied onto the interconnect microarchitecture. A key finding from this modeling is that wearout in the CMP on-chip interconnect is correlated with lack of load observed in the NoC routers, rather than high load. A novel wearout-decelerating scheme in which routers under low load have their wearout-sensitive components exercised, without significantly impacting cycle time, pipeline depth, area or power consumption of the overall router is developed, which shows that the proposed design yields a 13.8x-65x increase in CMP lifetime.
